The scale and integration density of semiconductor integrated circuit devices have been increasing with the lapse of time and, following it, various circuit systems and various element layout methods have been developed and used. For example, a dynamic random access memory (DRAM) uses a differential sense system in which a pair of bit lines with the same number of memory cells connected thereto are input to a sense amplifier. The sense amplifier amplifies only the voltage difference between the pair of bit lines, thereby canceling equal noise voltages and thus amplifying only a signal. This achieves low noise so that a very weak signal appearing in one of the pair of bit lines from the selected memory cell is stably discriminated. However, the properties of this discrimination are deeply related to the positional relationship of the pair of bit lines with the sense amplifier. As major bit line layout methods, there are an open bit line layout (FIG. 11) and a folded bit line layout (FIG. 12).
In the open bit line layout shown in FIG. 11, a pair of bit lines to be differential inputs to each of sense amplifiers SA are arranged in upper and lower different memory cell arrays. Word lines from word drivers WD are orthogonal to the bit lines and a memory cell at an intersection between the corresponding word and bit lines is selected. In the figure, the memory cell size is, for example, 2F (length)×2F (width), i.e. 4F2. Herein, F is a feature size and is generally set to a minimum dimension and the memory cell size is given by the product (4F2) of the length (2F) and the width (2F). This open bit line layout is a cross-point memory cell array structure in which memory cells are disposed at all intersections between word lines and bit lines and thus it is possible to arrange small memory cells such as 4F2 or 6F2 memory cells that make it difficult to form passing word lines. Therefore, the size (area) of the memory cell array can be made small. However, since each pair of bit lines are arranged in the different memory cell arrays, noise generated in one of the memory cell arrays appears on only one of the bit line pair and thus the open bit line layout is weak against noise. Further, since a signal appears on all bit lines crossing the selected word line, the sense amplifiers are required as many as the number of bit lines for amplification for read, write, or rewrite.
On the other hand, in the folded bit line layout shown in FIG. 12, a pair of bit lines to be differential inputs to each of sense amplifiers SA are arranged in the same memory cell array. However, as shown in the figure, since memory cells can be disposed at only half of intersections between word lines and bit lines, it is necessary to pass superfluous word lines. Even if small memory cells such as 4F2 or 6F2 memory cells are arrayed, superfluous word lines are required therebetween in a memory cell array. Therefore, practically, relatively large memory cells such as 8F2 memory cells are arrayed so that the memory cell array area relatively increases. However, since each pair of bit lines are arranged in the same memory cell array, noise generated in one of memory cell arrays appears on both bit lines forming a pair and thus is canceled as in-phase signals. Therefore, the folded bit line layout is excellent in noise characteristics. Further, since each pair of bit lines are arranged in the same memory cell array, it is possible to share each sense amplifier by the memory cell arrays on the opposite sides with respect to the sense amplifier by adding switching transistors for switching connection of the bit lines to the sense amplifier. Therefore, it is possible to halve or reduce the sense amplifier area.
As described above, the open bit line layout can make the memory cell array small, but has the problem that it is weak against noise. On the other hand, the folded bit line layout is excellent in noise characteristics, but has the problem that the memory cell array cannot be made small. As prior art patent documents relating to the above-mentioned open bit line layout and folded bit line layout, there are JP-A-2007-5502 and JP-A-2001-332632.